Architecture development

The main goal of the architecture development is to configure both logic and interconnections according to technical requirements. The architecture consists of programmable logic blocks which implement logic functions, programmable routing that establishes a connection between logic blocks, and Input/Output blocks for external connections.

FPGA design

We use Hardware Description Languages (HDL) such as Verilog and VHDL to describe the device functionality. Embedded Development Kit (EDK) implementation tools and reusable IP cores help us save months of development time. With the help of C++, we compile the ‘logic function’ and define how the components should connect to each other, and what sort of logic they should perform as the data flows through.

FPGA verification

Once FPGA design is complete, it is loaded onto the FPGA simulation. We verify logical elements to make sure each block of code can correctly process simple stimuli and each signal interface is correctly connected. We use various debugging tools and instruments: signal generators, scope, spectrum and logic analyzers, etc.

The configuration of IP cores

We provide integration and connection of third-party IP cores or blocks of logic and customization of soft IP cores developed in Verilog or VHDL for custom FPGA and CPLD designs. The soft cores can include UART, CPU, Ethernet controllers, and PCI interfaces.

CPLD design

We suggest using CPLD for devices that use a conventional microcontroller or microprocessor but still require high-speed data processing for small tasks. CPLDs are much cheaper than FPGA, they operate at higher frequencies and enable high performance. They are also easier to route which means the compilation time is going to be faster than it would be with FPGA.